Mercurial Repositories > eric / file comparison
comparison: eric6/ThirdParty/Pygments/pygments/lexers/hdl.py
eric6/ThirdParty/Pygments/pygments/lexers/hdl.py
- changeset 7983
- 54c5cfbb1e29
- parent 7701
- 25f42e208e08
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| 7982:48d210e41c65 | 7983:54c5cfbb1e29 |
|---|---|
| 3 pygments.lexers.hdl | 3 pygments.lexers.hdl |
| 4 ~~~~~~~~~~~~~~~~~~~ | 4 ~~~~~~~~~~~~~~~~~~~ |
| 5 | 5 |
| 6 Lexers for hardware descriptor languages. | 6 Lexers for hardware descriptor languages. |
| 7 | 7 |
| 8 :copyright: Copyright 2006-2020 by the Pygments team, see AUTHORS. | 8 :copyright: Copyright 2006-2021 by the Pygments team, see AUTHORS. |
| 9 :license: BSD, see LICENSE for details. | 9 :license: BSD, see LICENSE for details. |
| 10 """ | 10 """ |
| 11 | 11 |
| 12 import re | 12 import re |
| 13 | 13 |
| 129 ], | 129 ], |
| 130 'import': [ | 130 'import': [ |
| 131 (r'[\w:]+\*?', Name.Namespace, '#pop') | 131 (r'[\w:]+\*?', Name.Namespace, '#pop') |
| 132 ] | 132 ] |
| 133 } | 133 } |
| 134 | |
| 135 def analyse_text(text): | |
| 136 """Verilog code will use one of reg/wire/assign for sure, and that | |
| 137 is not common elsewhere.""" | |
| 138 result = 0 | |
| 139 if 'reg' in text: | |
| 140 result += 0.1 | |
| 141 if 'wire' in text: | |
| 142 result += 0.1 | |
| 143 if 'assign' in text: | |
| 144 result += 0.1 | |
| 145 | |
| 146 return result | |
| 134 | 147 |
| 135 | 148 |
| 136 class SystemVerilogLexer(RegexLexer): | 149 class SystemVerilogLexer(RegexLexer): |
| 137 """ | 150 """ |
| 138 Extends verilog lexer to recognise all SystemVerilog keywords from IEEE | 151 Extends verilog lexer to recognise all SystemVerilog keywords from IEEE |
